1. Field of the Invention
The present invention relates to a driving circuit for a liquid crystal display which corrects the display position in a vertical direction to obtain an excellent display area.
2. Description of Related Art
A driving system for a conventional liquid crystal display will be hereunder described with reference to FIGS. 2 to 4. FIG. 2 is a block diagram of a conventional TFT (Thin-Film-Transistor) liquid crystal display, FIG. 3 is a diagram showing a conventional scan driving circuit, and FIG. 4 is an operation waveform diagram of the conventional scan driving circuit.
In the block diagram showing the conventional liquid crystal display of FIG. 2, reference numeral 101 represents a signal bus for transmitting display data and a synchronous signal which are supplied from a system (not shown), reference numeral 201 represents a liquid crystal controller, reference numeral 202 represents a signal driving circuit, reference numeral 203 represents a scan driving circuit, reference numeral 204 represents a power supply for supplying various voltages, and reference numeral 205 represents a TFT liquid crystal panel.
With respect to the signals output from the liquid crystal controller 201, reference numeral 206 represents a signal bus containing the display data and the synchronous signal to be transmitted to the signal driving circuit 202, reference numeral 207 represents an FLM (First Line Marker signal), reference numeral 208 represents a CL3 clock serving as an operating clock of the scan driving circuit 203, and reference numeral 209 represents a liquid crystal alternating signal M to be supplied to the power supply 204.
Reference numeral 210 represents a drain bus for transmitting a gray-scale voltage generated by the signal driving circuit 202 to the TFT liquid crystal panel 205. Reference numeral 211 represents a gate bus for setting each line of the TFT liquid crystal panel 205 to one of a selection status and a non-selection status on the basis of the scan driving circuit 203. With respect to the voltages generated by the power supply 204, reference numeral 212 represents a Vgon voltage which has a selection voltage level and is one voltage to be supplied to the scan driving circuit 203, reference numeral 213 represents a Vgoff voltage which has a non-selection voltage level and is another voltage to be supplied to the scan driving circuit 203, reference numeral 214 represents a common electrode voltage line for transmitting a common electrode voltage to the liquid crystal panel, and reference numeral 215 represents a gray-scale voltage to be supplied to the signal driving circuit 202.
In the TFT liquid crystal panel 205, the drain bus 210 and the gate bus 211 are arranged to cross each other in a matrix form, and a crossing portion serving as a pixel comprises a TFT 216 functioning as a switching element and a liquid crystal element 217. The gate electrode of the TFT 216 is connected to the gate bus 211 and the drain electrode of the TFT 216 is connected to the drain bus 210. Therefore, a source electrode 218 of the TFT 216 serves as one electrode of the liquid crystal element 217. A common electrode 219 serves as the other electrode of the liquid crystal element 217, and it is connected to the common electrode line 214.
FIG. 3 shows the detailed construction of the conventional scan driving circuit 203. As shown in FIG. 3, reference numerals 301-1 to 301-8 represent scan drivers, and the scan driving circuit is constructed by the eight scan drivers which can be HD66215 (Hitachi LCD controller/driver LSI data book: issued by Semiconductor Enterprise Department on March, 1994, p622-634). The conventional scan driving circuit is described on the assumption that the vertical resolution of the TFT liquid crystal panel 205 is equal to 768 lines. The scan driver HD66215 has 100 output terminals, and G701 to G768 are used for the scan driver 301-8.
In the scan driver 301-1, an FLM (First Line Marker) (207) signal is connected to the input enable signal terminal (DIO1). The input enable signal terminal (DIO1) of the scan driver 301-2 is connected to the output enable signal terminal (DIO4) of the scan driver 301-1 at the front stage. Likewise, in the scan driver 301-3 and the subsequent scan drivers 301, the input enable signal terminal (DIO1) is cascaded to the output enable signal terminal (DIO4) of the scan driver 301 at the front stage.
In all the scan drivers 301, the clock (CL) terminal is connected to the CL3 (208), the power supply terminals V1, V6 are connected to the selection voltage level Vgon, and the power supply terminals V5, VEE are connected to the non-selection voltage level Vgoff. All the alternating terminals (M) for realizing the alternation of the liquid crystal are set to a "high" level.
In the operating waveform diagram of the conventional scan driving circuit of FIG. 4, FLM represents the operating waveform of the first line marker signal 207, CL3 represents the operating waveform of the operating clock 208, EO1 represents the signal of the output enable signal terminal (DIO4) which is output from the scan driver 301-1, and Vg1 to Vg768 represent the operating waveform of the gate bus 211.
The detailed operation of the conventional liquid crystal display will be described with reference to FIG. 2.
The liquid crystal controller 201 converts the display data and the synchronous signal transmitted from the signal bus 101 to display data and a liquid crystal driving signal which are suitable for driving the TFT liquid crystal display. The display data and the liquid crystal driving signal which are to be supplied to the signal driving circuit 202 are transmitted through the signal bus 206, the liquid crystal driving signals to be supplied to the scan driving circuit 203 are transmitted through FLM:207 and CL3:208, and the signal to be supplied to the power supply 204 is transmitted through the alternating terminal M:209.
In the signal driving circuit 202, the display data which are transmitted through the signal bus 206 are successively taken in, and when the taking-in operation of the display data of one horizontal line is completed, the display data are converted to a gray-scale voltage corresponding to the display data of one horizontal data, and then output from the drain bus 210. This operation is repetitively performed line by line by the signal driving circuit 202.
In synchronism with the output operation of the gray-scale voltage through the drain bus 210 to the liquid crystal panel 205 by the signal driving circuit 202, the selection voltage is successively applied via the gate bus 211 in the scan driving circuit 203. The detailed operation of the scan driving circuit 203 will be described later. When the selection voltage (Vgon) is applied via the gate bus 211, the TFT 216 in the TFT liquid crystal panel 205 is set to a selection status, and the gray-scale voltage transmitted through the drain bus 210 is applied to the liquid crystal 217. The twisted angle of the liquid crystal is varied by an effective voltage applied to the liquid crystal 217, whereby the induced ratio of light is controlled to perform a gray-scale display.
Further, when the non-selection voltage (Vgoff) is applied via the gate bus 211, the TFT 216 in the TFT liquid crystal panel 205 is set to a non-selection status so that the voltage applied to the liquid crystal 217 is kept. By repeating this operation during one frame period, all the TFTs 216 are allowed to be selected. The scan driving circuit 203 as described above will be described in detail with reference to FIGS. 3 and 4.
The scan driving circuit 203 comprises the eight scan drivers 301-1 to 301-8 as shown in FIG. 3. When the FLM signal is input to the scan driver 301-1, the selection voltage (Vgon) is applied to the first gate line G1 in synchronism with the input of the CL3 clock. At this time, the non-selection voltage (Vgoff) is applied to the other gate lines from G2 to G768.
The above operation will be described in detail with reference to FIG. 4.
As described above, the FLM signal is set to a "high" level, and the selection voltage (Vgon) is supplied with the voltage waveform Vg1 via the first gate line G1 in synchronism with a fall (trailing edge) timing of the CL3 clock. Further, when the FLM signal is set to a "low level" and the CL3 clock is input again, in synchronism with the fall timing of the CL3 clock, the non-selection voltage (Vgoff) is supplied with the voltage waveform Vg1 via the first gate line G1 while the selection voltage (Vgon) is supplied with the voltage waveform Vg2 via the second gate line G2. Further, when the CL3 clock is input, in synchronism with the fall timing thereof, the non-selection voltage (Vgoff) is supplied with the voltage waveform Vg2 via the second gate line G2 while the selection voltage (Vgon) is supplied with the voltage waveform Vg3 via the third gate line G3.
By repeating the above operation, the selection voltage (Vgon) is successively applied to each gate line until the voltage waveform Vg100 of the 100-th gate line G100. When the selection voltage (Vgon) having the voltage waveform Vg100 is applied to the 100-th gate line G100, the output enable signal (EO1) of the scan driver 301-1 is set to a "high" level, and it is then input to the scan driver 301-2 at the subsequent stage. In the scan driver 301-2, when the output enable signal (EO1) is set to a "high" level and the CL3 clock is input, in synchronism with the fall timing of the CL3 clock, the selection voltage (Vgon) is supplied with the voltage waveform Vg101 of the 101-st gate line G101. Subsequently, the same operation as the scan driver 301-1 is carried out on the scan driver 301-2.
In the scan driver 301-3 and the subsequent scan drivers 301, when the output enable signal is input, the selection voltage (Vgon) is successively applied via the gate bus 211 in synchronism with the fall timing of the CL3 clock in the same manner as described above. By repeating this operation during one frame period, the selection voltage (Vgon) is supplied with all the gate buses 211. Therefore, all the TFTs 216 in the liquid crystal panel 205 are set to the selection status, whereby the gray-scale voltage transmitted from the drain bus 210 can be applied to the liquid crystal 217 of all the pixels.
When one frame period elapses, the FLM signal is set to a "high" level again, and in synchronism with the fall timing (trailing edge timing) of the CL3 clock, the selection voltage (Vgon) is supplied with voltage waveform Vg1 via the first gate line G1 while the non-selection voltage (Vgoff) is supplied with the waveforms via the second gate line G2 and the subsequent gate lines of the gate bus 211. By repeating this operation successively, the display data of each frame period can be displayed on the liquid crystal panel 205.
The problems of the conventional liquid crystal display system as described above will be next described with reference to FIGS. 5 and 6.
FIG. 5 is an operating waveform diagram of the conventional scan driving circuit, and FIG. 6 is a display example of the conventional liquid crystal display.
In FIG. 5, the meaning of each signal is identical to that of FIG. 4. However, in the following description, the generating interval of the FLM pulses is assumed to be shorter than that of the operating waveform of FIG. 4. In FIG. 6, display data are displayed at the upper portion on a screen, black data of a retrace period are displayed at the center portion on the screen, and the display data are also displayed at the lower portion on the screen again.
The timing chart of FIG. 4 is described on the assumption that the total line number in the vertical direction, that is, the number of the CL3 clocks from the "high" level status of FLM until the next "high" level status of FLM is equal to 768 or more. However, some problem would occur if the total line number in the vertical direction, that is, the number of the CL3 clocks from the "high" level status of FLM until the next "high" level status of FLM was equal to 768 or less as shown in FIGS. 5 and 6. In FIG. 5, it is assumed that the total line number in the vertical direction is equal to 765 lines, and thus it is 3 lines short with respect to the total line number of the liquid crystal panel 205.
In FIG. 5, since the FLM signal is set to "high" level when the selection voltage (Vgon) is supplied via the gate line G766, the selection voltage (Vgon) is supplied via the gate line G1 at the same time. If the gate line G1 is set to the selection status, the gray-scale voltage corresponding to the first line data of the display effectiveness data is transmitted through the drain bus 210. Therefore, the same data as display data which are displayed on the gate line G1 are also displayed on the gate line 766 and the subsequent lines, so that the data displayed at the upper portion on the screen are duplicatively displayed at the lower portion on the screen as shown in FIG. 6. Accordingly, there occurs a problem that an excellent display image cannot be obtained.